1. Field of the Invention
The present invention relates to a static type of semiconductor memory device, and more particularly, to a static type of semiconductor memory device including a boosting circuit for boosting the voltage of a word line higher than a power supply voltage.
2. Description of Related Art
Recent, semiconductor integrated circuits shift quickly to allow a low voltage operation, for example, 3.3 V operation or 3.0 V operation because of user needs and the increase of reliability of the semiconductor integrated circuits themselves. A static type of semiconductor memory device is not excluded and a manufactures develop such products of the low voltage operation specification.
The technique for boosting the potential of a word line higher than a power supply voltage in the static type of semiconductor memory device is reported by K. Kozuru, M. Ukita, S. Murakami, Y. Morooka, Y. Nishimura, K. Anami in "A Boost Circuit for Low Supply Voltage" (Proc. of the 1993 IEICE Spring Conference, C-622, p. 5-252).
In this technique, as shown in FIG. 1, the static type of semiconductor memory device includes a word line boosting circuit 102 for boosting up the power supply voltage V.sub.CC to a voltage V.sub.BST, a word line driving circuit 103 for driving a word line WL in accordance with an input address to supply the voltage V.sub.BST to the word line WL, a pair of bit lines DG1 and DG1* (this means the inverted signal of DG1), and a memory cell circuit 104 connected to the word line WL and the pair of bit lines DG1 and DG1* via transfer gates. The boosting circuit 102 generates the boosted voltage V.sub.BST from the power supply it voltage V.sub.CC to supply to the word line driving circuit 103. The circuit 103 supplies the boosted voltage V.sub.BST on the word line WL in accordance with the input address. The memory cell circuit 104 includes a memory cell and is accessed via the pair of bit lines DG1 and DG1* when the boosted voltage V.sub.BST is supplied to the word line W1.
The word line boosting circuit 102 is shown in FIG. 2 in detail. Referring to FIG. 2, the circuit 102 is constituted by an inverter 21 for inputting a signal .phi..sub.BST, a P-channel MOS transistor Q102 connected between the power supply voltage V.sub.CC line and the boosted voltage V.sub.BST line and a P-channel MOS transistor Q103 connected to the boosted voltage V.sub.BST line, an N-channel MOS transistor Q104 connected between the P-channel MOS transistor Q103 and the ground potential, and a boosting up capacitor C.sub.BST between the output of the inverter 121 and the boosted voltage V.sub.BST line. Note that a parasitic capacitor C.sub.PAR is the capacitor parasitizing the boosted voltage V.sub.BST line. The signal .phi.BST is connected to the node between the gates of the MOS transistors Q103 and Q104 and the gate of the MOS transistor Q102 is connected to the MOS transistors Q103 and Q104. When the signal .phi..sub.BST is in the high level, the output of the inverter 121 is the low level so that the capacitor C.sub.BST is charged from the power supply voltage V.sub.CC via the P-channel MOS transistor Q102. When the signal .phi..sub.BST is in the low level, the output of the inverter 121 is the high level, so that the potential of the capacitor C.sub.BST is arisen higher than the power supply voltage V.sub.CC. FIG. 6 shows a relation of the boosted voltage V.sub.BST, i.e., the word line voltage to the power supply voltage V.sub.CC. As seen from the figure, the boosted voltage V.sub.BST becomes greater as the power supply voltage V.sub.CC is increased.
The above-mentioned word line driving circuit 103 is shown in FIG. 3 in detail. Referring to FIG. 3, the driving circuit 103 is constituted of a NAND circuit 131 for inputting an address signal and a word line activation signal .phi..sub.WL, an N-channel MOS transistor Q105 connected to the output of the NAND circuit 131 and having the gate always supplied with the power supply voltage V.sub.CC, a P-channel MOS transistor Q106 connected between the boosted voltage V.sub.BST line and the MOS transistor Q105 on the opposite side of the NAND circuit 131 and a P-channel MOS transistor Q107 connected to the boosted voltage V.sub.BST line and the word line WL, and an N-channel MOS transistor Q108 connected between the word line WL and the ground potential GND. The gate of the MOS transistor Q106 is connected to the word line WL and the gates of the transistors Q107 and Q108 are connected to the transistor Q105 together with the transistor Q106. When the word line WL is selected in accordance with the address signal and the activation signal .phi..sub.WL, i.e., when the output of the NAND circuit 131 is the low level, the N-channel MOS transistor Q108 is turned off so that the boosted voltage V.sub.BST is supplied to the word line WL through the P-channel MOS transistor Q107. On the other hand, when the word line WL is not selected, i.e., when the output of the NAND circuit 131 is the high level, the N-channel MOS transistor Q108 is turned on and the P-channel MOS transistor Q106 is also turned on. Therefore, the P-channel MOS transistor Q107 is turned off so that the word line WL is in the ground or low level.
FIG. 4 is a diagram showing an equivalent circuit of a typical memory cell circuit for storing memory information in the static type of semiconductor memory device. In the figure, a load resistor R101 is connected to the drain of an N-channel MOS transistor Q110 and the gate of an N-channel MOS transistor Q112, and a load resistor R102 is connected to the drain of the N-channel MOS transistor Q112 and the gate of the N-channel MOS transistor Q110. The sources of the N-channel MOS transistors Q110 and Q112 are connected to the ground potential. As a result, a flip-flop circuit is constituted. The node N1 between the load resistor R101 and the drain of the N-channel MOS transistor Q110 and the node between the load resistor R102 and the drain of the N-channel MOS transistor Q112 are connected to the bit lines DG1 and DG1* through the N-channel MOS transistors Q109 and Q111 as transfer gates, respectively. The gates of the N-channel MOS transistors Q109 and Q111 are connected to the word line WL. By arranging as described above, data of "1" or "0" can be arbitrarily stored at the nodes N1 and N2. In this case, the write operation or read operation to or from the nodes N1 and N2 are performed by setting the word line WL in a high level and selecting the bit lines DG1 and DG1*.
Whether or not the low voltage operation is allowed in the write operation in the static type of semiconductor memory device is determined based on a low voltage operation margin. For instance, in a case where data of "1" is written in the memory cell shown in FIG. 4, the power supply voltage V.sub.CC is applied to the word line WL and the bit line DG1 and a ground voltage GND is applied to the bit line DG1*, if the boosting circuit 102 is not present. In this case, the potential of the node N1 changes to a level of (V.sub.CC -V.sub.TN) immediately after the voltage is applied, where V.sub.TN is a threshold voltage of the N-channel MOS transistor Q109 or Q111 as the transfer gate. When a sufficiently long time (of an order of ms to sec.) elapses after the write operation, the potential of the node N1 reaches the V.sub.CC level by the load resistor R101 in the memory cell. In the normal operation (shorter than 10 nS), however, the potential is kept to be in the level of about (V.sub.CC -V.sub.TN). Therefore, in the low voltage operation, i.e., when the power supply voltage is low, the low voltage operation is further difficult, because the influence of the threshold voltage V.sub.TN to the write level becomes greater in relation to the power supply voltage V.sub.CC. Therefore, by employing the word line boosting circuit 102 as in the conventional static type of semiconductor memory device shown in FIG. 1, the voltage of word line WL can be boosted higher than the power supply voltage V.sub.CC, so that the large low voltage operation margin is allowed. As a result, the potential of the storage node N1 immediately after the write operation can be increased.
The operation of the conventional static type of semiconductor memory device including the word line boosting circuit 2 will be described below with reference to FIG. 5. FIG. 5 shows the operation waveforms in the conventional static type of semiconductor memory device. Referring to FIG. 5, first, at time 0, since the signal .phi..sub.BST is in the V.sub.CC level, the P-channel MOS transistor Q103 of the word line boosting circuit 102 is in the off state, and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 are in the on state. Accordingly, the boosted power supply voltage V.sub.BST is charged up to the V.sub.CC level. Next, at time t1, the signal .phi..sub.BST starts to be inverted from the V.sub.CC level to the ground (GND) level. In response to the signal .phi..sub.BST, the P-channel MOS transistor Q103 gradually changes to the on state and the P-channel MOS transistor Q102 and the N-channel MOS transistor Q104 gradually change to the off state. At the same time, the output of the inverter 121 starts to rise from the GND level toward the V.sub.CC level. That is, the potential of the boost up capacitor C.sub.BST starts to rise upwardly from the V.sub.CC level. Accordingly, the boosting up effect appears at the time t2. The boosting up operation is performed until the boosted voltage reaches the voltage of (V.sub.CC +V.alpha.) at the time t3. Note that V.alpha. varies based on a ratio of boost up capacitor C.sub.BST and parasitic capacitor C.sub.PAR. If C.sub.BST &gt;&gt;C.sub.PAR, is approximately equal to the power supply voltage V.sub.CC.
Next, a word line activation signal .phi..sub.WL changes from the GND level to the V.sub.CC level at the time t4. In response to the change of the signal .phi..sub.WL, the P-channel transistor Q107 of the word line driving circuit 103 goes to the on state and the P-channel MOS transistor Q106 and the N-channel MOS transistor Q108 goes to the off state. The voltage of the word line WL rises from the time t5 and reaches the voltage of (V.sub.CC +V.alpha.) at the time t6.
As described above, in the conventional static type of semiconductor memory device, if the ratio of the boost up capacitor C.sub.BST and the parasitic capacitor C.sub.PAR is set out of a target range because of the variation of the manufacturing process, the boosted voltages V.sub.BST of the word lines also arises. Therefore, it is difficult to adjust the boosted voltage V.sub.BST of the word line to a predetermined target voltage. If the ratio of the boost up capacitor C.sub.BST to the parasitic capacitor C.sub.PAR is changed because of variation of the manufacturing process, there would be cases wherein the word line is boosted higher or lower than the predetermined voltage. In the case where the boosted voltage of the word line WL is lower than the target voltage, the voltage of storage node is lower than the power supply voltage V.sub.CC immediately after the write operation, so that the low voltage operation margin is decreased. On the other hand, in the case where the boosted voltage of the word line WL is higher than the target voltage, the voltage of storage node is approximately equal to the power supply voltage V.sub.CC immediately after the write operation. However, the low voltage operation margin would be decreased. For this reason, the manufacturing process must be determined with a great margin.
Further, even if the boosted voltage V.sub.BST of the word line can be adjusted to the predetermined voltage, it is difficult to apply the semiconductor memory device to a power supply such as battery whose voltage varies, because the boosted voltage V.sub.BST of the word line is not constant over the wide range of power supply voltage.